LAUGHTON ELECTRONICS |
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One-bit Computing at 60 Hertz |
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This
page describes a tiny computer made from an EPROM and a few logic
chips. Its specifications are ridiculously modest, but the machine
readily satisfied application requirements. You may find that it
offers some insights and some amusement.
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 Click to enlarge  1 of 256 four-byte EPROM entries |
This
is a design I came up with in response to a customer's request to add
an automated function to some printing presses. The new behavior wasn't
complicated, but I wanted to use programmable logic instead
of hardwired gates, counters, and flip-flops. (Later when I
was asked to repeat the job I used a microcontroller.) It was the Motorola MC14500 that introduced me to the idea of one-bit computing. Eventually I discovered that the 14500 itself could be omitted, and that even its tiny complement of 16 instructions was overkill for some jobs. In contrast to the 14500's 4-bit op-code, my design uses no op-code at all. That's because there's only one instruction and it executes endlessly. It performs two functions: an Output operation, and an Input Test which selects the destination for a two-way branch. The schematic and instruction format are shown at left. Each instruction follows a two-phase cycle. An I/O byte is fetched from the EPROM during Phase One, and a Jump Destination byte is fetched on Phase Two. I/O bytes are actually stored in pairs, but one byte will be fetched and one will be ignored. The same is true for Jump Destination bytes. The choice is determined by the Flag Bit. During Phase 1 the EPROM reads one of the two I/O bytes (either the one at the address ending in 00 or 01) according to whether the Flag Bit is True or False. The I/O byte contains fields specifying both an input and an output. The output operation copies its one-bit Output Data field to any one of the 4099's eight Output Addresses (following a pipeline delay). The input operation reads one of the 4051's eight Inputs Addresses and copies the result to the Flag Bit. During Phase 2 the EPROM reads one of the two Jump Destination bytes (at 10 or at 11), according to the newly updated Flag. The jump takes effect at the start of the next cycle, updating the eight Most Significant Bits of the EPROM address to indicate the next four-byte entry. This one-bit wonder is adequate for a range of applications, although the coding takes some getting used to. Usually I coded the True and False I/O bytes to be identical, making the Flag a "don't care" for the I/O that occurs in Phase 1. Even in Phase Two I didn't necessarily need the Jump Destination to be a two-way branch, so sometimes the True and False Jump Destination fields were identical. The design features no memory as such; the only means to store a bit of information is to either branch the program into two paths or else write the data bit to a dedicated 4099 output which connects back to a 4051 input so it can be read back when needed! (The schematic shows two such I/O-mapped memory bits.) Also notable on the schematic are an RC filter to de-glitch the input line, and a Reset circuit that selects from the EPROM a shadow array of 256 unconditional "Jump to Start" instructions. The clock oscillator can optionally be altered to derive a square wave from the AC power line. (The choice of an extremely low operating frequency was simply to assist me in implementing a software time delay.) Two bits are unused on the lower 74C374 register; one of these could be wired so as to double the machine's Input or Output space or even, with careful attention to timing, the program space; alternatively a smaller (16 pin) 74C174 could replace the '374. On the 4099 addressable latch one bit is unconnected but "reserved" as a Write-Only-Memory; this is in lieu of a NOP or any other means to prevent an output operation when none is desired. |
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